The present invention relates to a high withstand voltage insulated gate N-channel field effect transistor having a withstand voltage of 15 V or more at a semiconductor substrate which can incorporate a Bipolar or CMOS and on which an epitaxial layer is formed, and to a semiconductor device including this high withstand voltage insulated gate N-channel field effect transistor.
FIG. 5 is a sectional view of an example of BiCMOS integrated circuits, which is manufactured by using a P-type semiconductor substrate 1 and through an N-type epitaxial step. An N-channel insulated gate field effect transistor 101 is formed in such a manner that a P-type well layer 4 is formed in an N-type epitaxial layer 2 and it is formed in this region, and a P-type insulated gate field effect transistor 102 is formed in a region of the N-type epitaxial layer 2. An NPN vertical bipolar transistor 103 is manufactured in such a manner that a P-type base region 15 and an N-type sinker 14 are formed in the N-type epitaxial layer 2 on an N-type buried layer 13. Separation of each element, especially separation between the insulated gate field effect transistor and the bipolar transistor can be made in such a manner that a P-type buried layer 3 and the P-type well layer 4 are made to be diffused from the upside and downside of the N-type epitaxial layer and are brought into contact with each other.
Although the thickness of the N-type epitaxial layer depends on the performance of an objective integrated circuit, as an example, when the withstand voltage of the NPN vertical bipolar transistor is set at 15 V or more, it is appropriate that the thickness is made 4 xcexcm or more. With respect to the N-type sinker 14, for the purpose of lowering collector resistance and lowering h fe of a parasitic bipolar, it is appropriate that the concentration is selected from the condition of 5xc3x971017 to 1xc3x971019/cm3 and the depth is selected from the condition of 3 to 5 xcexcm.
FIG. 2 is a sectional view of an example of a high withstand voltage insulated gate N-channel field effect transistors used at a semiconductor substrate including an epitaxial layer in a BiCMOS integrated circuit.
Reference numeral 1 denotes a semiconductor substrate, and a P-type semiconductor substrate is generally used. An N-type epitaxial layer 2 of 1xc3x971014 to 1xc3x971016/cm3 is formed on this P-type semiconductor substrate, and elements are formed therein. In the case of the N-channel insulated gate field effect transistor, a P-type well layer 4 and as the need arises, a P-type buried layer 3 are in this P-type region. Reference numerals 5 and 6 denote a source region and a drain region of the insulated gate field effect transistor, in which P or As is implanted to make the concentration as high as 1xc3x971020/cm3 or more. Although a gate electrode 8 is formed over a channel forming region 11 through a gate insulating film 7, and an N-type low concentration region 9 of 1xc3x971016 to 1xc3x971018/cm3 is formed between the drain region 6 and the channel forming region 11 so that a withstand voltage between the drain and source can be raised as compared with the case where this low concentration region does not exist. This is because a depletion layer at a drain side is apt to extend in this low concentration region as compared with a general insulated gate field effect transistor so that there is an effect to suppress the avalanche breakdown from occurring in the junction between the drain region and the channel forming region. Although the length of this low concentration region depends on a desired withstand voltage, it is appropriate that the length is set between 1.5 xcexcm and 3 xcexcm in the case where the withstand voltage is from 15 V to 40 V. When the insulating film 10 on the N-type low concentration region is made thicker than the gate insulating film, it is possible to avoid occurrence of a high electric field between the gate and drain, and it is possible to prevent a leak and breakdown due to this. It is desirable that the thickness of this insulating film 10 thicker than the gate insulating film is 0.1 xcexcm or more, and, for example, a field insulating film for separating elements may be used as the film.
However, the high withstand voltage insulated gate field effect transistor having the structure of FIG. 2 has a low ESD (Electric Static Discharge) strength and has a defect that when a drain terminal is connected to an external pad, junction breakdown is apt to occur in the N-type low concentration region by static electricity entering the drain terminal from the outside. In order to prevent the breakdown by the static electricity, for example, there is a method in which a specific protective element is provided at a wiring line communicating with a pad in a circuit. However, by setting this protective element, the area of a semiconductor integrated circuit is increased, and the cost is increased. For the purpose of improving the ESD strength of the high withstand voltage insulated gate field effect transistor without using the protective element, for example, there is a method in which a deep N-type diffusion region 12 is formed around the center of a high concentration drain region as shown in FIG. 4. However, this method also increases the cost due to the increase of steps since a mask step and a diffusion step must be newly added to form the N-type diffusion region. The higher the concentration of the N-type diffusion layer 12 is, and the deeper the depth from the surface of the N-type epitaxial layer 2 is, the better the ESD strength can be increased. For example, in the case of HBM (H man Body Model), in order to obtain an ESD strength of 2 kV or more, it is appropriate that the concentration of the N-type diffusion layer is 1xc3x971016/cm3 or more and the depth is 1.5 xcexcm or more.
As described above, in the high withstand voltage insulated gate field effect transistor, for the purpose of making the high withstand voltage compatible with the high ESD strength, it is impossible to avoid the increase of steps for one mask.
Then, for the purpose of solving such a problem of the prior art, an object of the present invention is to make the high withstand voltage and high ESD strength of a high withstand voltage insulated gate field effect transistor compatible with each other without using a protective element and without increasing lubrication steps.
In order to solve the above problem, according to the present invention, a high withstand voltage insulated gate N-channel field effect transistor is characterized by comprising: a source region and a drain region, each having an N-type and high concentration, formed on an N-type epitaxial layer formed on a P-type semiconductor substrate with an interval; a channel forming region between the source region and the drain region; a gate electrode formed through the channel forming region and a gate insulating film; an N-type low concentration region formed between the drain region and the channel forming region; an insulating film formed on the low concentration region and is thicker than the gate insulating film; a P-type buried-layer formed in a region, which is a boundary between the semiconductor substrate and the epitaxial layer, including the source region, the drain region, the channel forming region, and a region under the insulating film thicker than the gate insulating film; and a P-type well layer in a region including the source region, the channel forming region, and a part of the region under the insulating film thicker than the gate insulating film, and surrounding the drain region.
Further, the high withstand voltage insulated gate N-channel field effect transistor of the above-described structure is characterized in that the P-type well layer and the P-type buried layer are formed in a region including the source region, the channel forming region, and a part of the region under the insulating film thicker than the gate insulating film, and surrounding the drain region.
Further, the high withstand voltage insulated gate N-channel field effect transistor of the above-described structure, comprising a P-type buried layer formed in a region, which is a boundary between the semiconductor substrate and the epitaxial layer, including the source region, the channel forming region, and a part of the region under the insulating film thicker than the gate insulating film, and surrounding the drain region; and a P-type well layer formed in a region including the source region, the drain region, the channel forming region, and a region under the insulating film thicker than the gate insulating film, is characterized in that an N-type diffusion region with a concentration of 5xc3x971017 to 1xc3x971019/cm3 and a depth of 3 to 5 xcexcm is formed in a region including the drain region and a part of the region under the insulating film thicker than the gate insulating film.
Further, the high withstand voltage insulated gate N-channel field effect transistor of the above-described structure, comprising: an insulating film that is thicker than the gate insulating film, and formed between the source region and the gate insulating film, and between the drain region and the gate insulating film; an N-type low concentration region under the insulating film thicker than the gate insulating film; and a P-type buried layer in a region, which is a boundary between the semiconductor substrate and the epitaxial layer, including the source region, the drain region, a region under the gate insulating film; and a region under the insulating film thicker than the gate insulating film, is characterized in that the P-type well layer is formed, apart from the ends of the source region side and the drain region side of the gate insulating film, in a part of the region under the gate insulating film.
Further, the high withstand voltage insulated gate N-channel field effect transistor of the above-described structure, is characterized in that the P-type well layer and the P-type buried layer are formed, apart from the ends of the source region side and the drain region side, in a part of the region under the gate insulating film.
Further, the high withstand voltage insulated gate N-channel field effect transistor of the above-described structure is characterized in that the depth of the N-type region comprising an N-type epitaxial layer surrounded by the P-type buried layer and the P-type well layer, is not less than 2.5 xcexcm.
Further, the high withstand voltage insulated gate N-channel field effect transistor of the above-described structure is characterized in that the depth of an N-type region comprising the N-type epitaxial layer surrounded by the P-type semiconductor substrate, the P-type buried layer, and the P-type well layer, is not less than 2.5 xcexcm.
Further, the high withstand voltage insulated gate N-channel field effect transistor of the above-described structure is characterized in that the concentration of the N-type low concentration region is not less than 3xc3x971017/cm3, distances between the P-type well layer formed in a part of the region under the gate insulating film and respective ends of the gate insulating film on the source region side and on the drain region side are equal to each other, and the length thereof is 2.2 to 4.2 xcexcm each.
Further, the high withstand voltage insulated gate N-channel field effect transistor of the above-described structure is characterized in that the concentration of the N-type low concentration region is not less than 3xc3x971017/cm3, distances between the P-type well layer and the P-type buried layer formed in a part of the region under the gate insulating film and respective ends of the gate insulating film on the source region side and on the drain region side are equal to each other, and the length thereof is 2.2 to 4.2 xcexcm each.